As integrated circuit technology advances, demands for increased packing density, low power dissipation per square centimeter and compatibility between the various technologies increases. High packing density, usually obtained through device shrinkage, requires highly sophisticated processing techniques such as E-beam lithography, reactive ion etching, transient annealing, etc. However, in addition to these techniques, additional techniques are necessary to further reduce size, thereby reducing the required silicon overhead.
One type of device widely utilized in MOSFET circuits is a current source. The current source is conventionally fabricated by either connecting the gate of a transistor to the source thereof or the gate to the drain thereof. This results in a two terminal device. In conventional layout design, this element, although requiring only two terminals, consumes the same area as a three terminal transistor in addition to the area required to connect the gate to the doped drain or source. In conventional fabrication of the current source, buried source and drain regions are disposed on either side of a channel region which is covered by the gate. A polycrystalline silicon layer is then wrapped around from the gate to either the source or the drain. Therefore, a current source is merely a modification of the three terminal device with no savings in silicon overhead.
In view of the above disadvantages with present layout techniques for current sources, there exists a need for improved methods for fabricating a current source to minimize the silicon overhead.